A major goal in the design and manufacture of electronic circuitry is to increase the accuracy and precision of the operation of integrated circuits. In some instances the accuracy and precision of an integrated circuit may be increased by minimizing the error that is present in an input signal to an amplifier circuit. For example, consider the operation of a switching power supply circuit such as a direct current (DC) to direct current (DC) switching regulator. A block diagram of an exemplary prior art voltage mode compensation switching power supply circuit 100 is illustrated in FIG. 1.
The precision of voltage mode compensation switching power supply circuit 100 is limited by the accuracy of the internal voltage reference (VREF) and the input errors to the pulse width modulation (PWM) error amplifier 110. These errors are primarily due to the input referred offset voltage of PWM error amplifier 110 and the bandgap error amplifier 120. The source of these errors is well documented and understood.
This particular problem is much worse with complementary metal oxide semiconductor (CMOS) amplifiers because the matching of the CMOS transistors is significantly poorer than the matching of similarly sized bipolar transistors. This is particularly the case for CMOS transistors that are biased at low currents.
These offset errors (and the resulting temperature drift) can significantly affect the output accuracy of a switching power supply circuit. These offset errors may decrease the accuracy from a level of one percent (1%) over temperature to a level of five percent (5%) over temperature. The importance of accuracy requirements is continually increasing as power supply voltages continue to decrease. This is an application that is especially well suited for CMOS transistor switching power supply circuits.
The switching power supply circuit 100 shown in FIG. 1 can be thought of as a controlled switch with a duty cycle equal to the ratio of the output voltage (VOUT) to the input voltage (VIN). In switching power supply circuit 100 the ramp generator 130 creates a periodic waveform. The PWM error amplifier 110 drives the feedback voltage (VFB) to be equal to the reference voltage (VREF) by modulating the percentage of time that the switch (S1) is on during each period.
As previously mentioned, the duty cycle (in the steady state) will be very near the value of the ratio of output voltage to the input voltage (i.e., VOUT/VIN). The offset voltage of the PWM error amplifier 110 directly impacts the accuracy of the switcher output voltage (VOUT). The offset voltage of the PWM error amplifier 110 appears as an error of the reference voltage (VREF).
The primary source of error in the reference voltage (VREF) is due to the bandgap error amplifier 120 that is used to drive the bandgap core. The problem is again much worse in CMOS transistor switching power supply circuits because of the previously mentioned poor matching of CMOS transistors and because of a lack in many technologies of quality 3 terminal bipolar transistors (that have improved matching characteristics).
FIG. 2 is a block diagram illustrating a prior art complementary metal oxide semiconductor (CMOS) bandgap voltage reference circuit 200. CMOS bandgap voltage reference circuit 200 comprises terminal bipolar transistors Q1 and Q2. In the example shown in FIG. 2, resistor R1 has a value of five and seven tenths kilohms (5.7 kΩ). Resistor R2 has a value of fifty six and six tenths kilohms (56.6 kΩ). Resistor R3 also has a value of fifty six and six tenths kilohms (56.6 kΩ). In this example, the emitter area of transistor Q1 is nine (9) times the emitter area of transistor Q2.
CMOS bandgap voltage reference circuit 200 illustrates how a basic CMOS bandgap voltage reference circuit with an error amplifier (A1) having five millivolts (5 mV) of offset will be mis-biased by approximately forty seven millivolts (47 mV) at the reference output. That is, a five millivolt (5 mV) offset voltage (VOS) in the error amplifier (A1) creates a forty seven millivolt (47 mV) error at the bandgap voltage output (VBG). Even a small offset voltage in the error amplifier (A1) can cause a big error in the bandgap voltage (VBG). This, in turn, can cause a poor voltage reference temperature coefficient because the bandgap is not biased at the correct voltage for the ideal temperature coefficient.
There are always initial errors due to the mismatch between the critical matching transistors of the error amplifier (A1) and the resulting degraded temperature performance. In addition to these initial errors, there are also very significant errors attributed to the assembly shift of the integrated circuit chip. It seems that the assembly stresses create offset voltages in CMOS amplifiers on the order of (or even greater than) five millivolts (5 mV) at a two sigma level. This assembly shift is simply a change in the matching of those same critical transistors that had an impact on the initial input offset voltage. The errors that result at the reference output voltage are very significant because the bandgap design multiplies those errors by almost a factor of ten (10) depending on the ratio of the emitter areas of transistors Q1 and Q2. Similarly, the errors that result in the input offset voltage of the PWM error amplifier are also significant.
The problem to be solved is one of removing or reducing the errors in the output voltage (VOUT) of switching power supply circuit 100 by removing or reducing the errors from the offset voltages that are due to the PWM error amplifier 110 and the bandgap error amplifier 120.
There have been a number of prior art approaches to this problem. The various prior art approaches all attempt to improve the overall accuracy of switching power supply circuit 100 by reducing the input offset voltage errors that are caused by the PWM error amplifier 110 and the bandgap error amplifier 120. In each case an attempt was made to reduce the offset voltage to a value of voltage that was as close as possible to zero volts.
One such prior art approach employs laser trimming to trim out the offset errors. Laser trimming is somewhat effective but requires some circuit element to trim such as thin film resistors or metal links. Laser trimming adds circuit complexity and potentially adds process complexity. Another disadvantage of laser trimming is that it requires the added cost and the added manufacturing complexity of the laser trim operation. The laser trim operation is performed on a finished wafer.
Another disadvantage of laser trimming is that it does not eliminate the assembly stress contribution to the offset error. The assembly stress contribution can be almost as large as the initial offset errors. Unless the circuit elements are tested over temperature, there is no provision for correcting (or even detecting) those circuit elements with poor temperature drift performance. That means that all circuit elements must be tested over temperature in order to find the bad circuit elements.
Another prior art approach employs electrically erasable programmable read only memory (EEPROM) trimming. The EEPROM trimming method is an improvement in that the trimming process can be carried out post package. This eliminates the assembly shift component of the error. A major disadvantage is that EEPROM trimming requires additional manufacturing steps and additional cost. There is a significant amount of circuit complexity in an EEPROM memory array. In addition, the EEPROM trimming method does not address temperature performance. Test time and test cost is also an issue with the EEPROM trimming method. Some type of test mode is required in order to “bring out” the offsets so that they can be trimmed with the EEPROM trimming method.
Another prior art approach employs switched capacitors. In a switched capacitor technique the offsets of the amplifiers are “zeroed out.” In a switched capacitor technique the error is held on a capacitor and is then subtracted out. The switched capacitor technique has the advantage of taking care of offset over temperature. A major disadvantage is that the switched capacitor technique requires large capacitors, a clock and a sequencing or control circuit to manage the auto-zero operation. The sizes of the required capacitors can be very significant and can prohibit the auto-zero technique from being employed in circuits that are either cost sensitive or area sensitive (or both). In addition, in the switched capacitor technique, noise is aliased down in frequency and creates some jitter on some types of circuits.